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1. An effective cache overlapping storage structure for SMT processors SCOPUS EI 期刊论文 会议论文 认领

作者:He L.;Liu Z.

作者全称:He, Liqiang;Liu, Zhiyong

作者机构:[He, Liqiang ;Liu, Zhiyong ] Institute of Computing Technology, Chinese Academy of Sciences, Beijing, 100080, China;[He, Liqiang ] College of Computer 更多

第一作者:He, Liqiang

通讯作者:He, L.(hlq@ict.ac.cn)

通讯作者地址:He, L.; Institute of Computing Technology, Chinese Academy of Sciences, Beijing, 100080, China; 电子邮件: hlq@ict.ac.cn

来源:Proceedings - Fourth Annual ACIS International Conference on Computer and Information Science, ICIS 2005,2005,Vol.2005

基金:Korea Information Processing Society, KIPS;Int. Assoc. for Comput. and Info. Science, ACIS;Inst. of Info. Technol. Assessment, IITA, Korea

摘要:Simultaneous Multithreaded (SMT) processors improve the instruction throughput by allowing fetching and running instructions from several threads simu 更多

更新时间:Mar 28, 2019
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